1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which automatically carries out a refresh operation inside the device without requiring an external refresh command, and reads data during the refresh operation while attending to error correction.
2. Description of the Related Art
In DRAMs (dynamic random access memories), data are read from memory cells corresponding to a selected word line, and are amplified by sense amplifiers, followed by supplying data from the sense amplifier of a selected column to the exterior of the device. A DRAM is typically provided with a plurality of data input/output pins DQ, which outputs a plurality of data bits simultaneously. In order to reduce electric power consumption associated with access operations and to reduce the chip size by reduction of the number of wire lines, the plurality of DQ pins are associated with a single column line rather than associating a single DQ pin with a single column line. Namely, a plurality of sense amplifiers are connected to a single column line, and data of these sense amplifiers are input/output in parallel from/to the plurality of DQ pins.
For the purpose of speeding up the operation speed of semiconductor memory devices, generally, the operation of core circuits inside the memory devices need to be made faster. It is difficult, however, to speed up the operation of core circuits because of limitations such as wire delays. When a fixed number of data bits are to be serially input/output upon a single access, provision may be made not only to read data corresponding to the plurality of DQ pins in parallel from the memory core, but also to read serially output data in parallel from the memory core, then subjecting the data to parallel-and-serial conversion to arrange them sequentially along a time axis. With this provision, the data transfer rate to the exterior of the device can be improved without changing the operation speed of a core circuit. In detail, each column line is associated with a plurality of DQ pins, and a plurality of column lines are simultaneously activated that are equal in number to the number of data bits to be arranged along the time axis upon a single access, thereby reading the sequential data through parallel access.
FIGS.1A and 1B are drawings showing data read operations in a case in which a column line is activated when each column line is associated with a plurality of DQ pins and in a case in which a plurality of column lines are activated when each column line is associated with a plurality of DQ pins.
In FIG. 1A, each column line is assigned to DQ0 and DQ1, and a single column line is selectively activated to output data to the DQ0 pad and the DQ1 pad simultaneously. At a first cycle, a column line C1 is activated to output first data along the time axis. At a second cycle, a column line C2 is activated to output second data along the time axis.
In FIG. 1B, each column line is assigned to DQ0 and DQ1, and a plurality of column lines are simultaneously activated to concurrently output respective data to the DQ0 pad and the DQ1 pad and sequentially output a plurality of data along the time axis. At the first and second cycles, the column lines C1 and C2 are activated to output data of the column line C1 at the first cycle and to output data of the column line C2 at the second cycle.
In DRAMs, there is a need to periodically refresh data that are stored in memory cells. During the period in which a refresh operation is carried out for a given memory block, read/write access to this memory block is generally not possible. There are schemes, however, that make it possible to perform a data access operation concurrently with a refresh operation, thereby improving the efficiency of semiconductor memory devices.
One of such schemes uses parity bits, and this scheme is taught by an invention (Japanese Patent Application No. 2000-368423) assigned to the assignee of the present application. A parity bit is calculated with respect to a plurality of DQ data bits, and these DQ data bits are stored in memory together with the parity bit. Here, the plurality of DQ data bits are stored in respective memory blocks, and the parity bit is stored in a parity-bit-storage-purpose memory block. At the time of data read operation, the plurality of DQ data bits are read from the respective memory blocks, and the parity bit is read from the parity-bit-storage-purpose memory block. A parity check is carried out based on the retrieved DQ data bits and the parity bit. If a parity error is detected during a refresh operation, a data bit retrieved from the memory block that is currently being refreshed is corrected, and, then, the DQ data bits are output.
No attempt has ever been made to apply this error correction function for a refresh operation based on the use of parity bit to the configuration of FIG. 1B.
Accordingly, there is a need for a semiconductor memory device that has an error correction function for a refresh operation in a configuration in which each address line is associated with a plurality of data bits, and a plurality of address lines are simultaneously activated.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor memory device according to the present invention includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m greater than 1) data pins, each of which continuously receives or outputs n (n greater than 1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, mxc3x97n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks, and a parity data comparison circuit which performs a parity check on m data pieces read from the m respective blocks corresponding to the m respective data pins and a parity bit read from a parity-purpose memory block, the parity check being performed separately with respect to each of the n data pieces.
The semiconductor memory device described above has a configuration in which each address selection line is responsible for a plurality of data pieces, and a plurality of address selection lines are simultaneously activated. In this configuration, the present invention performs a parity check on m data pieces read from the m respective blocks and a parity bit read from a parity-purpose memory block separately with respect to each of the n data pieces, thereby providing an error correction function for a refresh operation.
According to one aspect of the present invention, the semiconductor memory device described above further includes a mask circuit which masks a specific one of the n data pieces with respect to all the m data pins at a time of data writing. In this configuration in which each address selection line is responsible for the n data pieces, and the m address selection lines correspond to the m respective data pins, the parity check that is directed to the m data pieces can be performed properly even if one of the n data pieces is nonexistent.
According to the present invention, further, a semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m greater than 1) data pins, each of which continuously receives or outputs n (n greater than 1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, mxc3x97n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, n address selection lines which are connected to n respective blocks of the memory blocks corresponding to the n respective data pieces, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the n respective blocks and resulting in m data pieces corresponding to the m respective data pins being input/output to/from the corresponding one of the n respective blocks, a parity data comparison circuit which performs a parity check on the n data pieces read from the n respective blocks and a parity bit read from a parity-purpose memory block, the parity check being performed separately with respect to each of the m data pieces, and a mask circuit which masks a specific one of the m data pieces with respect to all the n data pieces at a time of data writing.
In this configuration in which each address selection line is responsible for the m data pieces, and the n address selection lines correspond to the n respective data pieces, the parity check that is directed to the n data pieces can be performed properly even if one of the m data pieces is nonexistent.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.